Design and Verification of Dual Port RAM using System Verilog Methodology

Abstract

This thesis presents the design and verification of a Dual-Port RAM (DPRAM) using System Verilog, an industry-standard language for hardware design and verification. The primary objective is to ensure the functional correctness of the DPRAM design under diverse operational scenarios through an efficient and reusable testbench environment. The research begins with a detailed analysis of DPRAM architecture, covering memory organization, control logic, and data integrity mechanisms. The RTL is developed in Verilog HDL, maintaining modularity and adherence to design standards. To verify the functionality of the design, a System Verilog-based testbench is implemented. Simulation results demonstrate successful functional verification, with high coverage metrics reflecting design stability and correctness. Waveform analysis provides insights into protocol compliance and performance evaluation. This work underscores the effectiveness of System Verilog-based verification environments in memory IP validation and proposes optimization techniques to enhance the verification methodology for Dual-Port RAM.