TIET Digital Repository

Thapar Institute of Engineering & Technology (TuDR)

Welcome to Thapar Institute of Engineering & Technology Digital Repository (TuDR).

TuDR is the digital asset management system which integrates the intellectual output in the form of research articles, PhD theses, and M.Tech / M.E. theses. TuDR facilitates the sharing and exchange of intellectual output of the university.

TuDR supports the management of scholarly resources of enduring value to Thapar University. Faculty members, students, and research scholars use TuDR services to share their intellectual work with the global academic community.

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Recent Submissions

PCB Assembling and Customer’s Defect Rate Reduction
(Thapar Institute of Engineering and Technology, Patiala, 2026-08-18) Pandey, Nilesh; Pandey, Rishikesh; Bhardwaj, Dinesh
This thesis investigates the PCB assembling and use of dual varistors in the Printed Circuit Board Assembly (PCBA) of double door refrigerator to improve the surge protection and make the circuit reliable. Power line fluctuations and external factors such as lightning can cause voltage surges, which can lead to malfunction, inefficiency, or even damage to electronic components. To counter these risks, the research proposes a new design, in which two varistors are connected in parallel between the power input and supply lines. This is a good way to clamp the excess voltage to help protect the sensitive circuits from the transient overvoltage's. Several critical aspects of the methodology are highlighted: The selection of varistors with the right voltage ratings, energy absorption capacity, and response parameters; Design of an optimized PCB layout which accommodates the dual varistor configuration within a compact package; and thorough simulation and testing under transient voltage conditions. Prototype testing has confirmed that the dual varistor system can effectively suppress voltage spikes and safeguard electronic devices. Cooperation with manufacturers is an essential aspect of development process, and it is important that the design is developed correctly in the production process, and that it meets Circuit Design Rules (CDR). This partnership guarantees precise assembly and compliance with industry safety standards, enabling reliable and reproducible results. The results highlight the dual varistor configuration's ability to improve resilience and longevity of the electronics for the refrigerator. This helps prevent failures and maintenance issues, and maintains overall stability throughout the system's life. Also, the investigation focuses on the solution's compatibility with the highly demanding safety and performance standards of the consumer electronics industry. The new design not only enhances the durability and reliability of contemporary refrigerators but also creates a scalable model for surge protection of other consumer appliances. The dual varistor system is an important step forward in protecting sensitive electronic systems, enabling the creation of powerful and efficient appliances that cater to the needs of a safety-conscious consumer.
Design and Implementation of A Python-Based Automation Framework For Analog And Mixed-Signal (AMS) Verification
(2026-07-28) Sharma, Shashi Kant; Rai, Mayank Kumar; Pattanayak, Arnab
The rapid growth in the complexity of mixed-signal integrated circuits has placed enormous demands on the analog and mixed-signal (AMS) verification process. Manual setup of testbenches, AMS Connect Files (AMSCFs), and simulation environments across multiple PVT corners is time-consuming and a significant source of inconsistency and error. This thesis presents the design and implementation of a Python-based automation framework that addresses these challenges in a systematic and integrated manner. The proposed framework automates key steps in the AMS verification flow: netlist parsing for top-module and pin extraction, duplicate module detection, testbench template generation, AMSCF generation across PVT corners, simulation control, and regression management. Built around Real Number Modeling, the tool currently parses SystemVerilog and Verilog-AMS netlists and integrates with the industry-standard simulators Cadence Xcelium and Spectre; extending this support to SPICE-based netlists is identified as a direction for future work. A graphical user interface (GUI) enables engineers to interact with the framework without requiring deep knowledge of the underlying implementation. The framework was validated on the netlist of the design under test, reducing full test environment setup time from one to two working days to a few minutes. A complete set of twenty-seven PVT corner AMSCF files was generated automatically, all verified to be syntactically correct, and the generated testbench template, with a One-Wire protocol instantiated, compiled successfully in Cadence Xcelium without manual correction. An AI agent built on LLM such as Claude Sonnet 4.6 was further integrated to generate protocolaware test sequences from natural language prompts, producing multi-step analog stimulus from a single description, though minor human review remained necessary for timing-critical parameters. These outcomes confirm that the proposed framework substantially reduces manual effort in AMS verification setup while remaining accessible to engineers across varying experience levels.
ATPG Pattern Generation and Simulation for Enhanced Fault Coverage with DFT Flow
(2026-08-07) Mehta, Sumit; Munjal, Amit
As the complexity of Very Large Scale Integration (VLSI) circuits continue to escalate, ensuring their reliability and correctness has become a paramount challenge. Manufacturing defects, even minor ones, can lead to complete system failure, making robust testing an indispensable part of the semiconductor production cycle. This thesis ad- dresses the critical need for efficient testing methodologies through the exploration of Design for Testability (DFT). The primary objective of this research is to develop and simulate Automatic Test Pattern Generation (ATPG) strategies to achieve enhanced fault coverage in complex digital circuits. The work begins with a comprehensive review of fundamental and advanced DFT techniques, including scan design, scan compression, and various fault models such as stuck-at and transition faults. The proposed methodology follows a structured DFT flow, starting from Register- Transfer Level (RTL) design and proceeding through synthesis and DFT insertion. This involves integrating testability structures like scan chains and BIST logic directly into the design to improve the controllability and observability of internal nodes. The core of the work focuses on leveraging these DFT structures for effective ATPG and simulating the generated patterns to validate their effectiveness in detecting manufacturing faults. The research aims to contribute to reducing test time and improving the overall quality and reliability of VLSI products.
Project report financial accounting system
(1994) Dhillon , Amitabh S.
Explainable AI- Driven Hybrid Framework for Liver Fibrosis Segmentation
(2026-07-20) Kumar, Amardeep; Singh, Ashima; Chaudhary, Kuntal
Accurate segmentation of cirrhotic liver tissue in T2-weighted MRI is important for quantitative analysis, diagnosis aid and treatment planning. However, this task is challenging for conventional segmentation models due to the presence of weak boundaries, heterogeneous texture and shape variability. Motivated by these difficulties, the present thesis proposes a hybrid deep learning framework which combines transformer-based global context modelling with convolutional feature extraction to improve segmentation performance and reliability. The proposed approach combines SegFormer-B2 and ResNet-50 in a single encoderdecoder architecture for 2D liver segmentation. Hyperparameter optimization was done using Optuna. The final model was trained with a combined loss function including binary cross-entropy, Dice loss, and boundary-aware supervision. To enhance interpretability, the model also generated Grad-CAM based explainability maps to visualize the regions influencing model predictions. The model evaluated the model on the CirrMRI600+ T2W 2D benchmark and compared it to several strong baselines. The experimental results indicated that the proposed model obtained a Dice score of 92.67% and mIoU of 86.57% on the test set, and the best validation Dice was 93.33%. The results presented here show that the hybrid architecture is able to capture semantic context as well as fine anatomical detail, resulting in accurate and robust liver segmentation. In addition, the explainability analysis confirmed that the model focused on clinically relevant regions, which increased trust in its predictions. Overall, the research shows that hybrid transformer-convolution architectures, combined with boundary-aware training and explainable AI techniques, offer a promising solution for reliable cirrhotic liver MRI segmentation.