TIET Digital Repository

Thapar Institute of Engineering & Technology (TuDR)

Welcome to Thapar Institute of Engineering & Technology Digital Repository (TuDR).

TuDR is the digital asset management system which integrates the intellectual output in the form of research articles, PhD theses, and M.Tech / M.E. theses. TuDR facilitates the sharing and exchange of intellectual output of the university.

TuDR supports the management of scholarly resources of enduring value to Thapar University. Faculty members, students, and research scholars use TuDR services to share their intellectual work with the global academic community.

Facilities at Thapar Institute of Engineering & Technology Digital Repository (TuDR):

  • The users of TuDR can search, download, and browse the collections of documents.
  • Publish & share electronic documents.
  • Provide views & comments.
  • For creating new Communities or Collections, mail to dspace@thapar.edu

Communities in DSpace

Select a community to browse its collections.

Now showing 1 - 5 of 8

Recent Submissions

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    Polycystic Ovary Syndrome (PCOS) Detection: Using Deep Learning Approaches for Images and Clinical Features
    (NA, 2026-09-04) Madaan, Arushi; Bajaj, Anu; Garhwal, Sunita
    The hormone disorder known as polycystic ovarian syndrome (PCOS) is most prevalent in women nowadays. The ovaries of women are directly impacted by this metabolic disorder, where numerous small sacs of fluid develop around the edges of the ovary, called cysts or follicles. Despite advancements in technology, the exact cause of PCOS still remains unknown. It takes a lot of work for the doctors to manually diagnose it from the ultrasound (US) images. For PCOS identification, a range of machine learning (ML), deep learning (DL) and image processing techniques were employed, that allowed for the identification of follicle counts and follicle size analysis. The current research on PCOS detection for image segmentation and classification, as well as clinical characteristics, was reviewed in this work. For this study, we utilised two different kinds of dataset: image data and clinical feature dataset. We proposed a transfer learning-based DL approach for classifying women with PCOS by using ultrasound images. InceptionV3 and ResNet50 models were used, which achieved accuracy rates of 99.68% and 97.5%, respectively. Numerous DL algorithms were applied on the clinical dataset using various feature selection techniques. The flower pollination algorithm (FPA), cuckoo search algorithm (CSA), and genetic algorithm (GA) are the nature-inspired feature selection algorithms that have been utilised in the study. The results of the proposed GA-based feature selection using an ensemble model were statistically tested with the existing algorithms using Analysis of variance (ANOVA) and the Tukey test, with a 94.58% accuracy, 97.48% precision, 83.76% recall, 90.08% F1-Score, and 99.09% specificity. The interpretability of the results is further ascertained by explainable artificial intelligence (XAI) techniques, i.e., LIME and SHAP. Overall, by using reliable and accurate prediction models, this work advances predictive analytics in PCOS diagnosis with the goal of assisting early diagnosis and well-informed decision-making processes.
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    A Comparative Study of Directed Testing vs UVM-Based Random Verification
    (2026-09-04) Gupta, Konika; Upadhyay, Rahul; Sharma, Ashu; Saxena, Saurabh
    In this thesis, both directed testing and constrained random verification using the Universal Verification Methodology (UVM) approach are considered for verifying the functionality of an Advanced Highperformance Bus Lite (AHB Lite) protocol design. With today’s SoCs being very complex in nature, there is a great need to choose a proper verification methodology to ensure that all aspects comply with the protocol. This research provides a solution for this challenge by implementing both approaches on an AHB Lite slave memory design and then analyzing their performance based on certain quantitative metrics.. The directed test methodology validates basic AHB transactions such as single transactions, WRAP4 burst increments, and write then read transactions with manual stimulus with static address and known data patterns. The methodology based on UVM-Universal Verification Methodology uses a complete verification environment with a transaction level sequence item with protocol constrained, agent with driver and monitor, automation reference model scoreboard, and functional coverage collection from covergroups. Constrained random test stimuli generation covers the legitimate transaction space in different seeds, aiming at scenarios not anticipated in directed tests. Both approaches are looked at using a few different factors like functional coverage percentage, code coverage, simulation throughput, test code volume, debugging complexity, and how well the testbench architecture scales. The results show that directed testing gives us a clear and easy way to debug known scenarios with just a bit of infrastructure. On the other hand, UVM-based constrained random verification manages to cover a lot more cases with fewer lines of test code, plus it brings to light some corner case behaviors that might get missed in tests that are written by hand. Overall, these findings are pretty useful for verification engineers when they're picking the right method for AHB-based digital IP verification in today's SoC development projects.
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    Constrained Random Verification of a Digital IP Using System Verilog
    (2026-09-04) Sood, Himanshi; Kumar, Ravi; Sharma, Saurabh
    This thesis describes the restricted random verification of a digital IP for an AXI4-Lite-based design with SystemVerilog. As advanced communication protocols are incorporated into contemporary SoC designs, it is crucial to guarantee the functional accuracy of AXI-compliant intellectual property. Conventional directed testing techniques frequently fall short in covering protocol-level interactions and corner cases. In order to increase coverage, scalability, and reusability, a limited random verification methodology is used. Developing a reusable and modular verification environment with SystemVerilog features like classes, randomization, constraints, assertions, functional coverage, and interfaces is the main goal of the effort. In order to validate address, data, and control channel transactions, an AXIbased digital IP is validated by producing random stimuli within specified protocol limitations. While assertions are used to verify protocol compliance and identify violations during simulation, functional coverage models are used to gauge the completeness of verification. The verification environment is designed to achieve great coverage and to find corner case bugs fast. The efficiency of limited random verification in enhancing design resilience and cutting verification time is shown by simulation results. In order to validate complicated AXIbased digital IPs for dependable SoC integration, this work emphasizes the significance of sophisticated verification approaches.
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    Modeling and Performance Analysis of Optical Interconnect for Emerging Nanoscale Technology Nodes
    (2026-09-03) Bharee, Amoldeep Singh; Sandha, Karmjit Singh; Rai, Mayank Kumar
    The continuous scaling of nanoscale VLSI systems has pushed conventional electrical interconnects, particularly Copper (Cu) and Carbon nanotube (CNT), to their performance limits as they approach ampacity limits. These limitations results in increased delay, higher power dissipation, and reduced thermal reliability. As technology nodes advance, these challenges intensify, creating a need for alternative interconnect solutions that offer higher bandwidth, lower latency, and improved energy efficiency. This thesis investigates Optical Interconnects (OIs) as a promising candidate for future global interconnect architectures and presents a comprehensive modeling and performance evaluation framework for emerging 22 nm and 14 nm CMOS nodes. The optical link model incorporates recent device-level advancements, including lowcapacitance modulators and photodetectors (50 fF), waveguide propagation characteristics, and detailed receiver behaviour. A key contribution of this work is the design of a high-speed optical receiver based on an Active Voltage Current Feedback (AVCF) based Regulated Gain Cascode (RGC) Transimpedance Amplifier (TIA) implemented in 0.18 µm CMOS technology. The inductorless TIA employs an RGC-based gain-boosting stage to enhance transconductance, reduce input resistance, and extend the bandwidth, followed by a common-source (CS) stage for additional gain. Analytical modeling and Cadence Virtuoso simulations validate the design, demonstrating a TIA gain of 62 dB−Ω, a bandwidth of 8.2 GHz, an input-referred noise density of 31 pA/√ Hz, and a power consumption of 14.5 mW. System-level comparisons of OI, Cu, and single-walled carbon nanotube (SWCNT-B) interconnects show significant performance advantages for OIs at global scales and beyond. At an interconnect length of 1000 µm and the 22 nm node, OIs demonstrate delay improvements of 88.47% over Cu and 62.15% over SWCNT-B interconnects. At 14 nm, these improvements increase to 93.68% and 84.29%, respectively. OIs also exhibit superior power efficiency beyond a critical interconnect length, with advantages that broaden as technology scales. To address thermal challenges in advanced nodes, this thesis develops a temperature aware modeling framework that accounts for variations in laser slope efficiency, threshold current, effective refractive index (ne f f), waveguide propagation loss, photodetector responsivity, and TIA transconductance over the range 300-500 K. SPICE simulations show that OIs maintain lower delay, reduced power dissipation, and improved power-delay product (PDP) under elevated temperatures compared to Cu and SWCNT-B interconnects. These results highlight the thermal resilience and scalability of OIs for future nanoscale VLSI communication systems. Overall, the proposed device to circuit modeling approach, high-speed TIA design, and comprehensive comparative analysis establish OIs as an energy-efficient, thermally robust, and scalable communication solution for next-generation integrated circuits (ICs).