TIET Digital Repository

Thapar Institute of Engineering & Technology (TuDR)

Welcome to Thapar Institute of Engineering & Technology Digital Repository (TuDR).

TuDR is the digital asset management system which integrates the intellectual output in the form of research articles, PhD theses, and M.Tech / M.E. theses. TuDR facilitates the sharing and exchange of intellectual output of the university.

TuDR supports the management of scholarly resources of enduring value to Thapar University. Faculty members, students, and research scholars use TuDR services to share their intellectual work with the global academic community.

Download Archive Request Form: (PDF) | (Word)
Submission Guidelines: Download Submission Guidelines

Facilities at Thapar Institute of Engineering & Technology Digital Repository (TuDR):

The users of TuDR can search, download, and browse the collections of documents.
Publish & share electronic documents.
Provide views & comments.
For creating new Communities or Collections, mail to dspace@thapar.edu

Communities in DSpace

Select a community to browse its collections.

Now showing 1 - 5 of 8

Central Library 6
Departments 4967
Research@TIET 68
Persons or groups engaged in research at TIET
Schools 1746
Sponsored Projects 4

Recent Submissions

Modeling and Performance Analysis of Optical Interconnect for Emerging Nanoscale Technology Nodes
(2026-09-03) Bharee, Amoldeep Singh; Sandha, Karmjit Singh; Rai, Mayank Kumar
The continuous scaling of nanoscale VLSI systems has pushed conventional electrical interconnects, particularly Copper (Cu) and Carbon nanotube (CNT), to their performance limits as they approach ampacity limits. These limitations results in increased delay, higher power dissipation, and reduced thermal reliability. As technology nodes advance, these challenges intensify, creating a need for alternative interconnect solutions that offer higher bandwidth, lower latency, and improved energy efficiency. This thesis investigates Optical Interconnects (OIs) as a promising candidate for future global interconnect architectures and presents a comprehensive modeling and performance evaluation framework for emerging 22 nm and 14 nm CMOS nodes. The optical link model incorporates recent device-level advancements, including lowcapacitance modulators and photodetectors (50 fF), waveguide propagation characteristics, and detailed receiver behaviour. A key contribution of this work is the design of a high-speed optical receiver based on an Active Voltage Current Feedback (AVCF) based Regulated Gain Cascode (RGC) Transimpedance Amplifier (TIA) implemented in 0.18 µm CMOS technology. The inductorless TIA employs an RGC-based gain-boosting stage to enhance transconductance, reduce input resistance, and extend the bandwidth, followed by a common-source (CS) stage for additional gain. Analytical modeling and Cadence Virtuoso simulations validate the design, demonstrating a TIA gain of 62 dB−Ω, a bandwidth of 8.2 GHz, an input-referred noise density of 31 pA/√ Hz, and a power consumption of 14.5 mW. System-level comparisons of OI, Cu, and single-walled carbon nanotube (SWCNT-B) interconnects show significant performance advantages for OIs at global scales and beyond. At an interconnect length of 1000 µm and the 22 nm node, OIs demonstrate delay improvements of 88.47% over Cu and 62.15% over SWCNT-B interconnects. At 14 nm, these improvements increase to 93.68% and 84.29%, respectively. OIs also exhibit superior power efficiency beyond a critical interconnect length, with advantages that broaden as technology scales. To address thermal challenges in advanced nodes, this thesis develops a temperature aware modeling framework that accounts for variations in laser slope efficiency, threshold current, effective refractive index (ne f f), waveguide propagation loss, photodetector responsivity, and TIA transconductance over the range 300-500 K. SPICE simulations show that OIs maintain lower delay, reduced power dissipation, and improved power-delay product (PDP) under elevated temperatures compared to Cu and SWCNT-B interconnects. These results highlight the thermal resilience and scalability of OIs for future nanoscale VLSI communication systems. Overall, the proposed device to circuit modeling approach, high-speed TIA design, and comprehensive comparative analysis establish OIs as an energy-efficient, thermally robust, and scalable communication solution for next-generation integrated circuits (ICs).
PCB Assembling and Customer’s Defect Rate Reduction
(Thapar Institute of Engineering and Technology, Patiala, 2026-08-18) Pandey, Nilesh; Pandey, Rishikesh; Bhardwaj, Dinesh
This thesis investigates the PCB assembling and use of dual varistors in the Printed Circuit Board Assembly (PCBA) of double door refrigerator to improve the surge protection and make the circuit reliable. Power line fluctuations and external factors such as lightning can cause voltage surges, which can lead to malfunction, inefficiency, or even damage to electronic components. To counter these risks, the research proposes a new design, in which two varistors are connected in parallel between the power input and supply lines. This is a good way to clamp the excess voltage to help protect the sensitive circuits from the transient overvoltage's. Several critical aspects of the methodology are highlighted: The selection of varistors with the right voltage ratings, energy absorption capacity, and response parameters; Design of an optimized PCB layout which accommodates the dual varistor configuration within a compact package; and thorough simulation and testing under transient voltage conditions. Prototype testing has confirmed that the dual varistor system can effectively suppress voltage spikes and safeguard electronic devices. Cooperation with manufacturers is an essential aspect of development process, and it is important that the design is developed correctly in the production process, and that it meets Circuit Design Rules (CDR). This partnership guarantees precise assembly and compliance with industry safety standards, enabling reliable and reproducible results. The results highlight the dual varistor configuration's ability to improve resilience and longevity of the electronics for the refrigerator. This helps prevent failures and maintenance issues, and maintains overall stability throughout the system's life. Also, the investigation focuses on the solution's compatibility with the highly demanding safety and performance standards of the consumer electronics industry. The new design not only enhances the durability and reliability of contemporary refrigerators but also creates a scalable model for surge protection of other consumer appliances. The dual varistor system is an important step forward in protecting sensitive electronic systems, enabling the creation of powerful and efficient appliances that cater to the needs of a safety-conscious consumer.
Design and Implementation of A Python-Based Automation Framework For Analog And Mixed-Signal (AMS) Verification
(2026-07-28) Sharma, Shashi Kant; Rai, Mayank Kumar; Pattanayak, Arnab
The rapid growth in the complexity of mixed-signal integrated circuits has placed enormous demands on the analog and mixed-signal (AMS) verification process. Manual setup of testbenches, AMS Connect Files (AMSCFs), and simulation environments across multiple PVT corners is time-consuming and a significant source of inconsistency and error. This thesis presents the design and implementation of a Python-based automation framework that addresses these challenges in a systematic and integrated manner. The proposed framework automates key steps in the AMS verification flow: netlist parsing for top-module and pin extraction, duplicate module detection, testbench template generation, AMSCF generation across PVT corners, simulation control, and regression management. Built around Real Number Modeling, the tool currently parses SystemVerilog and Verilog-AMS netlists and integrates with the industry-standard simulators Cadence Xcelium and Spectre; extending this support to SPICE-based netlists is identified as a direction for future work. A graphical user interface (GUI) enables engineers to interact with the framework without requiring deep knowledge of the underlying implementation. The framework was validated on the netlist of the design under test, reducing full test environment setup time from one to two working days to a few minutes. A complete set of twenty-seven PVT corner AMSCF files was generated automatically, all verified to be syntactically correct, and the generated testbench template, with a One-Wire protocol instantiated, compiled successfully in Cadence Xcelium without manual correction. An AI agent built on LLM such as Claude Sonnet 4.6 was further integrated to generate protocolaware test sequences from natural language prompts, producing multi-step analog stimulus from a single description, though minor human review remained necessary for timing-critical parameters. These outcomes confirm that the proposed framework substantially reduces manual effort in AMS verification setup while remaining accessible to engineers across varying experience levels.
ATPG Pattern Generation and Simulation for Enhanced Fault Coverage with DFT Flow
(2026-08-07) Mehta, Sumit; Munjal, Amit
As the complexity of Very Large Scale Integration (VLSI) circuits continue to escalate, ensuring their reliability and correctness has become a paramount challenge. Manufacturing defects, even minor ones, can lead to complete system failure, making robust testing an indispensable part of the semiconductor production cycle. This thesis ad- dresses the critical need for efficient testing methodologies through the exploration of Design for Testability (DFT). The primary objective of this research is to develop and simulate Automatic Test Pattern Generation (ATPG) strategies to achieve enhanced fault coverage in complex digital circuits. The work begins with a comprehensive review of fundamental and advanced DFT techniques, including scan design, scan compression, and various fault models such as stuck-at and transition faults. The proposed methodology follows a structured DFT flow, starting from Register- Transfer Level (RTL) design and proceeding through synthesis and DFT insertion. This involves integrating testability structures like scan chains and BIST logic directly into the design to improve the controllability and observability of internal nodes. The core of the work focuses on leveraging these DFT structures for effective ATPG and simulating the generated patterns to validate their effectiveness in detecting manufacturing faults. The research aims to contribute to reducing test time and improving the overall quality and reliability of VLSI products.
Project report financial accounting system
(1994) Dhillon , Amitabh S.