Design of a high speed and low power sense amplifier

Abstract

Sense Amplifier is one of the most important part of the memory. It is used to access the stored data in bit cell during read cycle. Sense amplifier amplifies the small difference between bitlines to the full swing level. Its performance affects the access time and power dissipation of memory and hence by reducing the sensing delay and power consumption of sense amplifier the performance of memory improves. A 6T SRAM has been designed using Cadence Spectre 5.1.4 1_ISR for the various sizes of transistors to store the data and to retrieve the data from it. The layout of 6T SRAM has been also designed to calculate the bitline capacitance of a bit cell using Cadence Virtuoso 5.1.4 1_ISR layout editor and for RC extraction of layout Cadence Assura 3.2.0 is used. The different circuits of sense amplifiers such as cross coupled, clamped bitline, latch type and hybrid type are studied and compared. On basis of different circuits of sense amplifiers a new high speed and low power sense amplifier has been designed at 0.18 µm technology. Extensive results at 0.18 µm CMOS technology using Cadence Spectre 5.1.4 1_ISR simulation tools have been observed for different sense amplifier circuits. The sensing delay of different types of sense amplifiers are evaluated with respect to variation in bitline capacitance and variation in power supply. The average power for different values of bitline capacitance has been also analyzed. From these results it has been observed that delay of sense amplifier circuit is dependent mainly on the capacitance of the bitlines from the memory cell. By isolating these bitline capacitances the sensing delay can be reduced very much. The comparison of designed sense amplifier has been carried out with the different types of sense amplifiers using 0.18 µm technology. The designed sense amplifier has been about 40-80% faster than other sense amplifiers.