Analysis, Verification and FPGA Implementation of Vedic Multiplier With Bist Capability

Abstract

This thesis work is devoted for the design of a high speed Vedic multiplier, its implementation on reconfigurable hardware and Built in Self Testing (BIST) of the implemented multiplier. Interfacing of FPGA with a PS2 KEYBOARD has also been done. For arithmetic multiplication various Vedic multiplication techniques like Urdhva tiryakbhyam, Nikhilam and Anurupye has been thoroughly discussed. It has been found that Urdhva tiryakbhyam Sutra is most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers, either small or large. Further, the Verilog HDL coding of Urdhva tiryakbhyam Sutra for 32x32 bits and 64x64 bits multiplication and their FPGA implementation by Xilinx Synthesis Tool on Spartan 3E kit have been done. The input of Vedic multiplier has been given by a PS2 KEYBOARD and output has been displayed on LCD of Spartan 3E kit. The synthesis results show that the computation time for calculating the product of 32x32 bits is 7.784 ns, while for the product of 64x64 bits is 10.241 ns. Finally, the implemented design has been tested by using Built in Self Test, which shows that this Vedic multiplier is completely fault free.