Low Power & Process Variation Resistant SRAM Design Using Process Tracking & VTCMOS

Abstract

In the light of exponentially increasing number of microprocessor based devices like smartphones, tablets, laptops and Internet of Things (IoT) devices, reducing power consumption of portable device is major area of interest. Static Random Access Memory (SRAM) is an integral part of a System On Chip(SOC) and consumes a significant area on the die. Thus reducing power consumption is an indispensable part of SRAM design for portable devices. Another concern for SRAM design is increased process variability in deep sub-micron technology. Process variations not only make SRAM functionally fail in form of read/write errors but also leads to increased power dissipation in faster process corners. This thesis presents the concept of dynamically identifying the operating process condition of the integrated circuit and implement the corrective measures by using Variable Threshold Complementary Metal Oxide Semiconductor (VTCMOS) scheme to 6-Transistor SRAM (6TSRAM) cell. A ring oscillator is used as process sensor that operates at a frequency which is characteristic of a particular process corner. A digital circuit called process decoder has been designed which reads the operating process corner from the process sensor. It identifies the process corner of the SRAM cell and generates a control signal which is fed to the voltage control block. The voltage control block provides the body bias voltage for the NMOS transistors of the SRAM cell. This setup results in reduced power dissipation and enhanced resistance to process variations.