Modeling and Performance Analysis of Optical Interconnect for Emerging Nanoscale Technology Nodes

Abstract

The continuous scaling of nanoscale VLSI systems has pushed conventional electrical interconnects, particularly Copper (Cu) and Carbon nanotube (CNT), to their performance limits as they approach ampacity limits. These limitations results in increased delay, higher power dissipation, and reduced thermal reliability. As technology nodes advance, these challenges intensify, creating a need for alternative interconnect solutions that offer higher bandwidth, lower latency, and improved energy efficiency. This thesis investigates Optical Interconnects (OIs) as a promising candidate for future global interconnect architectures and presents a comprehensive modeling and performance evaluation framework for emerging 22 nm and 14 nm CMOS nodes. The optical link model incorporates recent device-level advancements, including lowcapacitance modulators and photodetectors (50 fF), waveguide propagation characteristics, and detailed receiver behaviour. A key contribution of this work is the design of a high-speed optical receiver based on an Active Voltage Current Feedback (AVCF) based Regulated Gain Cascode (RGC) Transimpedance Amplifier (TIA) implemented in 0.18 µm CMOS technology. The inductorless TIA employs an RGC-based gain-boosting stage to enhance transconductance, reduce input resistance, and extend the bandwidth, followed by a common-source (CS) stage for additional gain. Analytical modeling and Cadence Virtuoso simulations validate the design, demonstrating a TIA gain of 62 dB−Ω, a bandwidth of 8.2 GHz, an input-referred noise density of 31 pA/√ Hz, and a power consumption of 14.5 mW. System-level comparisons of OI, Cu, and single-walled carbon nanotube (SWCNT-B) interconnects show significant performance advantages for OIs at global scales and beyond. At an interconnect length of 1000 µm and the 22 nm node, OIs demonstrate delay improvements of 88.47% over Cu and 62.15% over SWCNT-B interconnects. At 14 nm, these improvements increase to 93.68% and 84.29%, respectively. OIs also exhibit superior power efficiency beyond a critical interconnect length, with advantages that broaden as technology scales. To address thermal challenges in advanced nodes, this thesis develops a temperature aware modeling framework that accounts for variations in laser slope efficiency, threshold current, effective refractive index (ne f f), waveguide propagation loss, photodetector responsivity, and TIA transconductance over the range 300-500 K. SPICE simulations show that OIs maintain lower delay, reduced power dissipation, and improved power-delay product (PDP) under elevated temperatures compared to Cu and SWCNT-B interconnects. These results highlight the thermal resilience and scalability of OIs for future nanoscale VLSI communication systems. Overall, the proposed device to circuit modeling approach, high-speed TIA design, and comprehensive comparative analysis establish OIs as an energy-efficient, thermally robust, and scalable communication solution for next-generation integrated circuits (ICs).