FPGA Implementation of Efficient Modified Booth Wallace Multiplier

Abstract

The multiplication operation is present in many parts of a digital system or digital computer, most notably in signal processing, graphics and scientific computation. With advances in technology, various techniques have been proposed to design multipliers, which offer high speed, low power consumption and lesser area. Thus making them suitable for various high speed, low power compact VLSI implementations. These three parameters i.e. power, area and speed are always traded off. This thesis work is devoted for the design of a low power high-speed Booth Wallace multiplier and its implementation on reconfigurable hardware. For arithmetic multiplication, various multiplication architectures like array multiplier, Booth multiplier, Wallace tree multiplier and Booth Wallace multiplier have been thoroughly discussed. It has been found that Booth Wallace multiplier is most efficient among all, giving optimum delay, power and area for multiplication. Low power modified Booth recoder and pipelining techniques have been used to reduce power and delay. Further, the VHDL coding of Booth Wallace multiplier for 8x8 bit, 16x16 bit and 32x32 bit multiplication and their FPGA implementation by Xilinx Synthesis Tool on Spartan 3E kit have been done. The output has been displayed on LCD of Spartan 3E kit. The synthesis results show that the computation time for calculating the product of 8x8 bit is 8.78 ns, while for the product of 16x16 bit is 10.13 ns and 32x32 bit is 13.38ns.