Analytical Drain Current Model of Fully Depleted Silicon-On-Insulator MOSFET with Back-Gate Control

Abstract

SOI (Silicon-On-Insulator) technology has been acquiring a bundle of alertness and exercise in the integrated chip, and the portent of CMOS technology from a long decade while offering the superior performance with enhanced speed of operation and lowering the SCEs for sub-micron devices application in electronic industries. Recently, studies engross their concentration on Fully Depleted (FD) - SOI device due to their higher scalability relative to CMOS bulk technology and various new structures based on engineering techniques have been proposed. One of them is to design the model of an FDSOI with high k-dielectric material and with metal gate technology came into limelight for enhancing high drive current ratio. In this thesis, firstly on the basis of device physics the value of surface potential, threshold voltage and Electric field for an asymmetrical FDSOI MOSFET is derived by using 2-D Poisson equations, then by using charge-sheet based model the drain current for the device has evaluated. The model discussed the device operation of back-gate controlling the threshold voltage of the front-gate for all the region of operations that is Accumulation, Depletion or Inversion, and also the influence of buried oxide thickness, doping concentration on threshold voltage with respect to back-gate biasing has depicted. Then transfer characteristics have been examined while varying the back-gate voltage at different Drain-voltage and buried-Oxide Thickness. Simulation of the device has been performed using TCAD Co-genda tool. Results of an Analytical Model have reflected the similar agreement when compared with published and simulation results.