Pre Silicon RTL Verification of Mixed Signal IPs through Real Value Modelling

Abstract

Validation remains an unavoidable, yet truly difficult and prolonged part of Intellectual Property (IP) configuration and manufacture process. With shortening timelines and expanding time-to-market necessity, IP producing houses are compelled to put more resources into validation. Hence validation remains an indispensable and essential period of today's IP design and integration procedure. Validation techniques can be partitioned into two stages: pre-silicon validation and post-silicon validation. Pre-silicon validation refers to validation activities that has been performed on a simulation or emulation model prior to fabrication of actual silicon. Pre-silicon validation verifies the correctness and efficiency of the design. Verification of Mixed Signal IP has been always a major point of concern. Though Mixed Signal IP have both analog as well as digital part, verifying them individually have become a tedious task. For modern IP, a technique which provide fast solution for verification in pre-silicon stage is necessary. The verification has been done at pre-silicon stage to make post silicon stage bug free. Because verifying a design at post silicon stage takes a lot time and costly re-spin process. As time to market has become a crucial factor, a solution must be there with a verifying IP having both analog and digital block with checking behavior of analog block in a real manner. Verification of analog blocks have been done in digital environment which make simulation faster and get better performance. A methodology for verifying analog and mixed signal IP has been implemented through real value modelling. In this method, an analog block behavior has been cloned in a digital environment. This real value modelling has been done with the help of hardware verification language such as System Verilog with OVM methodology.