Design of Low Power High Performance SOI Dram Cell

Abstract

ABSTRACT In this thesis, the analysis and design of Dynamic Random Access Memory (DRAM) cell for low leakage have been done. For the analysis , fully-depleted SOI DRAM cell has been considered. For the design of fully-depleted SOI DRAM cell, an nMOSFET as access transistor and the floating body cell as a storage device have been considered at 30 nm process technology. Various DRAM cell structures such as three-transistor memory cell, one-transistor one-capacitor memory cell, capacitorless one-transistor floating body cell and two-transistor floating body cell have explored. Various leakage mechanisms, such as subthreshold leakage, Gate–induced drain leakage, punchthrough and PN junction reverse bias leakage for an access transistor have been focused. Process level techniques for leakage reduction, such as lightly doped drain, retrograde well and halo doping have been discussed and employed in the SOI DRAM cell. Process and device simulation of fully depleted SOI DRAM cell have been carried out using the ATHENA/ATLAS packages of SILVACO. The fully depleted SOI DRAM cell structure has been generated using ATHENA and then it is used as input to device simulator ATLAS for its electrical characterization. Leakage reduction from 2.25 nA to 10 pA in fully depleted SOI DRAM cell has been achieved using above mentioned process level techniques.