Design of a Low Power, 8-Bit, 5MS/s Digital to Analog Converter for Successive Approximation ADC

Abstract

DAC occupying small area capable of high resolution is of use in many applications. A monotonic DAC always has an increasing analog output with increasing digital input. Here, a switched capacitor DAC is presented that exhibits monotonicity while occupying a small area. The proposed DAC starts its conversion from MSB instead of the traditional approach of starting from LSB making it suitable for use in cyclic or successive approximation ADCs. The DAC samples the reference voltage only once and transfers appropriate charge to an output capacitor. Some issues relevant to the design and their possible solutions are presented. DAC is designed for 8-bit resolution. Sampling speed is chosen to be 5MS/s and main emphasis is on low power. This DAC consumes power in the order of microwatts. Switched capacitor DAC is designed and simulated in CadenceR Virtuoso Analog Design Environment using UMC 180nm technology to validate its performance. Layout of op-amp and DAC is made in CadenceR Virtuoso Layout XL Environment.