Design of Area and Power Efficiect N-Bit Digital Binary Comparator

Abstract

The design techniques aimed for the optimizations of the area, power and speed parameters of the digital circuits are used as the integral part in design process of any modern digital electronic device. To achieve the high speed and low power operation, an extensive research of such techniques is required. Proposed N-bit digital comparator designed with minimal number of transistors, can operate with high operating speed while dissipating limited power in any digital building block. With the advantages offered by it, it has presented itself as a promising substitute over other conventional comparator design approaches. In the proposed circuit Novel EX-OR-NOR logic cells are used for the power and area optimizations. The circuit intended for comparison of 64-bit operands has full input-output swing of 1.8V, maximum operating frequency of 1.75 GHz, worst case power dissipation of 1.03 mw/ GHz and requires total number of transistors as 1384 for its operation. The proposed circuit architecture have been designed and simulated in Cadence Virtuoso Design Environment using Gpdk 180 nm CMOS technology. The comparison of the proposed N-bit digital comparator with other comparator structures available in literature shows that the suggested comparator design can be used in the jitter measurements, built in self-test circuits, load-store queue buffers, etc.