High Performance Ternary Logic Design With CNTFETS for Future Nanoelectronics

Abstract

A viable substitute for conventional binary systems is ternary logic which provides higher data density, simpler circuitry, and possibly lower power consumption. In this work, we investigate the use of Carbon Nanotube Field-Effect Transistors (CNTFETs) for the implementation of ternary logic. Because of their superior electrical properties—such as high carrier mobility, excellent scalability, and low power dissipation—CNTFETs have become a promising candidate for next-generation Nano electronic devices. In this work ternary logic circuits of NAND and NOR and standard ternary inverter are develop and simulated while considering the CNTFET as a device. By choosing the right threshold voltages for the various states (0, 1, 2), the use of CNTFETs in ternary logic design provides improved tenability in addition to making circuits smaller and more energy-efficient. The simulation results further demonstrate the higher energy efficient. This work proposed new circuits of standard ternary logic gates, including the ternary inverter, ternary NAND, and ternary NOR, using CNTFET device. The proposed and existing circuits of these gates are simulated with 32nm CNTFET technology node using Synopsys HSPICE. The simulation results confirm the correct ternary behavior, where the ternary inverter follows Vout = 2 - Vin, the ternary NAND produces a high output unless both inputs are high, and the ternary NOR generates a low output when either input is high. Compared to existing designs, the proposed CNTFET-based ternary circuits demonstrate improved performance in terms of reduced power consumption, lower transistor count, and enhanced switching characteristics. These results validate the feasibility of CNTFET-based ternary circuits, paving the way for efficient ternary arithmetic circuit design for low-power VLSI applications.