Implementation and Optimization of PCI Target Device

Abstract

Cost is the most important factor taken into consideration while designing a chip, which mainly includes the design cost and manufacturing cost. Manufacturing cost depends upon the number of chips produced on a single wafer, thus it depends upon the size of the chip. Thus to reduce the chip size the designers are constantly looking for various technologies. Among these technologies, the reuse technology is widely adopted. In brief, the reuse is to design the circuit again in such a way that some parts can be repeatedly used in the circuit, and minimize the area of the circuit. In this thesis we have re-reused PCI AD bus and C/BE# bus to communicate with the master. We have designed two PCT Target Devices, one without implementing re-reuse technology and the other with re-reuse technology. The designs have been simulated and synthesized with 90 nm standard cell library on FPGA using Xilinx ISE and with 180 nm standard cell library on Synopsys Design Compiler. Synthesis results show that with implementing re-reuse technology on the time sharing basis, the I/O pin count can be reduced by 35 pins. Though we need to implement a slightly complicated logic due to which the design area has increased but as the feature size is decreasing very rapidly, an increase in gate count by few hundreds can be incorporated very easily.