Comparative Analysis of Various Cordic Techniques

Abstract

CORDIC is an acronym for COrdinate Rotation Digital Computer. The CORDIC method is the most versatile of all the algorithms that can be used to evaluate elementary functions. The same hardware can be used to compute trigonometric ratios (sin, cos, tan, etc.), hyperbolic ratios (sinh, cosh, tanh), multiplication, division, inverse trigonometric (arcsin, arccos) and inverse hyperbolic ratios (arcsinh, arccosh), with a slight modification it can also compute logarithms, exponentials, etc. In this work, it has been found that CORDIC algorithm requires 3 adders/subtractors and 3 registers. So it is multiplierless approach and it saves a lot of hardware and hence power dissipation is very low as compared to other methods. Due to the simplicity of the involved operations, the CORDIC algorithm is very well suited for VLSI implementation. In this work, CORDIC algorithm, pipeline CORDIC, control CORDIC and DFT (Discrete Fourier Transform) have been implemented in XILINX Spartan 3E FPGA kit using VHDL. The comparison of original CORDIC on the basis of their power, speed, area required to implement in chip designing, number of iteration etc. have been discussed. It has been found that as data rate increases, number of slices, flip-flops, LUTs, IOBs, power and delay have also increased. Look up tables have been used to compare precision for different data rates. It has been observed that resolution of CORDIC algorithm is best for 32 bit data rate. Original CORDIC algorithm does have one drawback however, in that the algorithm exhibits linear convergence, so that N iterations are required to converge to N bits of accuracy. When used in modern computing elements which operate at a high clock frequency, this large latency has a deleterious effect on overall system performance. In this work, the latency has been calculated to be equal to 8.191 ns for 12-bit original CORDIC algorithm. Latency can be further reduced by pipeline CORDIC. It has been found that latency is reduced by 34.97% using pipeline CORDIC as compared to Original CORDIC. It has also been observed that pipeline CORDIC reduces the number of resources by 7.5% as compared to original CORDIC. In addition to it, power dissipation in pipeline CORDIC has also been reduced by 6.74% as compared to original CORDIC. In this work, it has been found that Original CORDIC algorithm, the iteration variable ( i z ) does not always converge monotonically to 0Îsome of the iterations may actually result in divergent micro-rotations, which do nothing to improve the convergence towards the target vector. This problem has been solved using control CORDIC method which modifies the angle trajectory so that it now resembles a critically damped system, with no overshoot, resulting in faster convergence. The application of CORDIC has been shown using Discrete Fourier transforms (DFT). It has been found that in DFT implementation number of multiplier, adders/subtractors, registers, comparators are 4, 6/5, 121, 5 respectively. Due to high speed, low cost and greater flexibility offered by FPGAs over DSP processors, the FPGA based computing is becoming the heart of all digital signal processing systems of modern era.