Design and Implementation of All Digital Phase Locked Loop
| dc.contributor.author | Prabhakar, Prince | |
| dc.contributor.supervisor | Agarwal, Alpana | |
| dc.date.accessioned | 2017-08-11T11:50:25Z | |
| dc.date.available | 2017-08-11T11:50:25Z | |
| dc.date.issued | 2016 | |
| dc.description | M.Tech (VLSI Design) | en_US |
| dc.description.abstract | Phase Locked Loops (PLLs) are widely used in clock recovery and frequency synthesis. Fully Digital PLLs are more suitable for the monolithic implementation with other circuits compared to the traditional implementations of the PLLs. The All Digital PLLs are also independent of process variations and can be easily ported to different technologies. This thesis presents the design of an All-Digital Phase Locked Loop (ADPLL) using a twin Vernier delay line based time to digital converter and an All-Digital Lock Detection and Control Unit (ADLDC). General design criteria are summarized for the all-digital implementation in comparison to the traditional approaches and analog implementations. The design has been implemented using 0.18𝜇𝑚 CMOS technology. The ADPLL can operate in the frequency range between 230 MHz and 1.118 GHz the ADPLL has a lock time of 1.768𝜇𝑠. The simulation results of the ADPLL are also presented to verify its operation. | en_US |
| dc.description.sponsorship | SMDP-C2SD Project; Electronics And Communication Engineering Department | en_US |
| dc.identifier.uri | http://hdl.handle.net/10266/4651 | |
| dc.language.iso | en | en_US |
| dc.subject | ADPLL | en_US |
| dc.subject | PLL | en_US |
| dc.subject | Digital | en_US |
| dc.subject | All Digital | en_US |
| dc.subject | Synthesizable | en_US |
| dc.subject | Phase Locked Loop | en_US |
| dc.title | Design and Implementation of All Digital Phase Locked Loop | en_US |
| dc.type | Thesis | en_US |