Design and implementation of single precision floating point multiplier using divide and conquer technique

Abstract

Floating-point arithmetic is considered an esoteric subject by many people. This is rather surprising because floating-point is ubiquitous in computer systems. Almost every language has a floating-point data type; computers from PC’s to supercomputers have floating-point accelerators; most compilers will be called upon to compile floating-point algorithms from time to time; and virtually every operating system must respond to floating-point exceptions such as overflow. The advantage of floating-point representation over fixed-point (and integer) representation is that it can support a much wider range of values. A system’s performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the system. Floating point multiplication is much like integer multiplication. Because floating-point numbers are stored in sign-magnitude form, the multiplier needs only to deal with unsigned integer numbers. In this thesis, architecture for a fast floating point multiplier compliant with the single precision IEEE 754 standard floating point multiplier has been designed. Different multipliers are designed using Verilog. Divide & Conquer technique and pipelining technique are used to design floating point multipliers. The designs are simulated on Modelsim SE 6.3f and synthesized on Xilinx ISE 8.2i targeted on FPGA on device Spartan 3E xc3s500E. This dissertation pays a significant attention to the analysis of multiplier in terms of area and delay.