Design and analysis of a 14-bit low power SAR ADC

Abstract

Now a days most of communicating system require wireless signal that is in digital form but at the same time if talking about real world all systems output analogues in nature, due to this reason firstly to communicate with real world analog signal convert into digital signal. For this system first requirement is speed. This fact leads to designer or researcher to proposed and implement analog to digital converter. Successive approximation ADC is accepted for reasonable rapid conservation with fine resolution. This present work explains the 14-bit SAR ADC with sampling frequency 20MHz. This present work mainly focused on the digital to analog converter block of SAR ADC for high speed and resolving coupling effect of device. Proposed design simulated in cadence virtuoso analog design environment and analog mixed signal (AMS) in 180nm CMOS technology. It has been designed for sampling frequency 20MHz to achieve high resolution for 14- bit successive approximation register ADC. Supply voltage for this design is 1.8V caters effective number of bit is 13.86.