Design of Low Power CMOS Cell Structures Based on GATE Diffusion Input Technique

Abstract

From the day when first transistor was invented (in 1947), low area, low power, and high speed these are primary issue for a researcher in the transistor based technology. In present scenario the minimization of power consumption have emerged as a key design constraint over the last few years due to increasing demand of complex mobile system in the very large scale integrated circuit design. The battery operated devices which commonly used in present time, also require more portability, high power output with fast timining and cost in budget.

As there are many flexible design topologies like complementary CMOS, passtransistor logic, transmission gate based technology and so on, but we have no any design technique which provide required flexibility in low power design. So an approach is presented for minimizing power consumption for low power CMOS cell structure.

GATE DIFFUSION INPUT (GDI) technique is a believable step up in the world of low power VLSI design. The primary concern in this thesis work is the reduction of power dissipation using the Gate diffusion input technique with the design of CMOS cell structure and compare with CMOS based cell structure cell design. All these circuits were designed in IC station Cadence IC5141 using standard TSMC 0.18 μm technology. All the circuit simulations in this thesis have been done in a systematic process. From the schematic design of the structures to post-layout simulations using IC station Cadence IC5141. For the simulation, DRC, LVS, and POST-LAYOUT Assura is used which is a design verification suite of tools within the Virtuoso custom design platform. And then finally the powers have been taken for the various time period for both the design methods.