An Investigation of Flipped Voltage Follower Cells for Analog VLSI Circuits

Abstract

Nowadays, the use of battery-operated portable electronic devices has been rapidly increasing. The portability requirement demands low power dissipation to increase the battery's life and minimize the size of the battery. Low power becomes the major design constraint in the designing of battery-operated devices. These devices consist of analog and digital circuits integrated on a chip. The density of integrated circuits has been continuously increasing with the scaling down of complementary metal-oxide-semiconductor (CMOS) technology. To reduce the power dissipation and maintain the reliability of the integrated circuits, the supply voltage needs to be scaled down. In integrated circuits, the small-channel length and low supply voltage operation enhance the performance of the digital circuits in terms of speed, power, and integration. However, short channel effects and low supply voltage degrade the performance of analog circuits in terms of non-linearity in the output, which becomes the bottleneck of the system. This has forced the analog designers to switch from conventional analog circuit architectures to new low-voltage/low-power transistor implementation techniques. In the thesis, analog cells called flipped voltage follower (FVF) cells have been investigated to regain circuit performance in a low voltage environment. However, the conventional FVF cell shows class-A behaviour such that either the quiescent bias current is high or the settling time is poor, thus showing an asymmetrical slew rate. The output resistance of the class-A FVF cell is also not low enough. Class-AB biasing employed in the FVF cell can reduce its power consumption as the quiescent bias current can be kept at low value and symmetrical slew rate can be achieved with low output resistance. The thesis proposes four class-AB FVF cells namely class-AB FVF cell-I, class-AB FVF cell-II, class-AB FVF cell-III, and class-AB FVF cell-IV, which offer several improved electrical features such as current sourcing/sinking capability, output resistance, slew rate, input/output voltage swing, etc. as compared to existing FVF cells available in the literature. The analyses of proposed class-AB FVF cells have been performed using small-signal modelling. The proposed class-AB FVF cell-I uses the replica-biased scheme to eliminate the DC level shift between input and output voltages where the input voltage is applied at the bulk terminal. The class-AB FVF cell-I can provide approximately unity voltage gain with high current driving capability but it shows limited bandwidth because the input voltage is applied at the bulk terminal. In the proposed class-AB FVF cells (II and III), the input voltage is applied at the gate terminal and bulk driven transistor is used as an adaptable current source to enhance the current sourcing capability. The current sinking capability has been increased using an extra transistor and quasi-floating gate technique in class-AB FVF cells II and III, respectively. The class-AB FVF cell-IV uses the folding transistor to provide an alternate path for sourcing currents while reducing the output resistance. A level shifter has also been employed to increase the input/output voltage swing. The class-AB FVF cell-IV shows significantly better results in terms of various performance parameters than the other three proposed class-AB FVF cells and FVF cells available in the literature. To demonstrate the working of proposed class-AB FVF cells, these FVF cells have been used as the building blocks in designing a basic analog VLSI circuit, i.e. current mirror. The current mirrors I, II, III, and IV have been proposed using class-AB FVF cells I, II, III, and IV, respectively at the input stages and thus offer low input resistance due to class-AB FVF cells. The proposed current mirrors offer various improved electrical features such as input resistance, output resistance, current mirroring range, error, minimum input voltage, and minimum output voltage. All the proposed circuits have been designed using BSIM3V3 180 nm CMOS technology and simulated using spectre in the Cadence Virtuoso Analog Design Environment. The physical layouts of the proposed circuits have been designed using Cadence Virtuoso Layout XL editor in 180 nm CMOS technology.