Pre-Silicon Testchip (IO ring) validation

Abstract

The design and verification of Input/Output (IO) circuits play a crucial role in ensuring reliable communication between integrated circuits and external interfaces. This thesis presents the layout design and verification of a level shifter, focusing on layout strategies, and verification methodologies in CMOS technology. The final layout was verified through Design Rule Check (DRC) and Layout vs. Schemtic (LVS) validation using Cadence Layout Design Suite and Calibre, ensuring manufacturability and functional correctness. Additionally, the level shifter is an essential circuit for voltage translation between different power domains, especially in low-power and mixed-signal designs. The layout for the level shifter was designed from scratch using Cadence tools, following strict foundry guidelines. Rigorous DRC and LVS checks were performed using Calibre to confirm its correctness and adherence to fabrication constraints. This work highlights the importance of precise layout design and validation in IO circuit, reducing the chances of post-silicon failures and ensuring first-pass success in silicon fabrication. The successful completion of level shifter layout, and associated verification steps demonstrates the effectiveness of the adopted design methodologies. By presenting a practical implementation of level shifter design, this thesis keeps importance in validation of IO and bridges the gap between theoretical VLSI concepts and real-world design constraints, providing valuable insights for future IO circuit development.