Verification of Analog and Mixed Signal IPS using SV-UVM Verification Methodology

Abstract

UVM Based Verification (UVM) is one of the broadly utilized verification methodology to improve the verifying nature of Analog and Mixed flag IPs Design so as to accelerate the checking procedure. A confirmation domain to check the functionality of IP by utilizing System Verilog - UVM based approach. The functionality of Analog IPs was checked by Cadence Incisive and VCS tools. With Incisive and VCS Simulator, not only check the status of output pins by applying different input pattern but also reduce the overall debugging effort and shortened debug turnaround time. With the best possible test plan and verification plan checking the functionality of AMS IPs became simpler. The verification has been done at pre-silicon stage to make post silicon stage bug free. Because verifying a design at post silicon stage takes a lot time and costly re-spin process. As time to market has become a crucial factor, a solution must be there with a verifying IP having both analog and digital block with checking behavior of analog block in a real manner. Verification of analog blocks have been done in digital environment which make simulation faster and get better performance. Most frameworks on-chip (SoC) plans today are Mixed signal ones, and all SoCs will be mixed signal at cutting edge process hubs sooner rather than later. The fundamental objective of this project is to automate the UVM Environment and make the verification quick and simple.