Design of Low Power, Wide Linearity Range Differential Ring VCO with Power Down Technique

Abstract

Many electronic circuits and systems such as microprocessors and cognitive radios use a PLL to generate the accurate clock. VCOs are the critical blocks in Phased Locked Loops (PLLs) and various VCO based ADCs as it impact the performance and consumes the most of their power budget. In the field of circuit and system designing, a suitable clock generation circuit plays an important role. For this purpose, VCOs are basic blocks as they consume most of the power consumed by the system itself. Hence the low power and low area VCOs has been always in demand for the researchers. To get the reliable performance of a ADC/PLL, VCO should be robust across the Corners. And in a VCO, achieving the wide tuning range is key concern according to different applications. This research work explains the low power and wide tuning range differential VCO with an in built power down technique in it. The new architecture is proposed in this work consists of voltage to current converter and NAND based ring oscillators. Also, a PVT compensation circuit is added to achieve better linearity across the different PVT corners. The proposed circuits mentioned above are simulated in Cadence Virtuoso Analog Design Environment in SCL 180 nm CMOS technology with a supply voltage of 1.8V. It has a linearity range from 0.9 V to 1.8 V and tuning range from 40 MHz to 650 MHz .The measured power consumption for this work is 50.4 nw/208.8 μW when power down switch is ON/OFF. The measured phase noise of this architecture is -130.1dBc/Hz at 1MHz offset frequency.