Power Efficient High DC Gain Adaptive Biased CMOS Operational Transconductance Amplifier

Abstract

The rapid increasing use of battery operated portable equipment in the application areas such as telecommunication and medical electronics have increased the importance of low power and small sized circuits realized with VLSI technology. The most efficient way to reduce power consumption is to decrease both the supply voltage and the stand-by current. Reduced supply voltage is not a favourable choice for analog design since it leads to several performance degradations because threshold voltage of MOS transistors does not scale well with the reduced supply. Therefore, current becomes more favourable than voltage as the information-carrying quantity in a low-voltage low-power environment. A circuit using current mode technique has many advantages such as larger dynamic range, higher bandwidth, greater linearity, simpler circuitry and low power consumption. Operational Transconductance Amplifier (OTA) is an important building block of current mode circuit in analog design. To achieve lower stand-by power consumption in OTAs by reducing stand-by current is a better choice. Adaptive biasing technique may be very useful in this context. Also high dc gain of the OTA is a very important parameter to ensure the performance of the whole system. However, it is becoming more and more difficult to obtain high dc gain of OTA with low voltage operation. Hence, the technique of partial positive feedback is explored which is a good way to boost the gain without speed penalty. In the dissertation, current adder, current subtractor and a Power Efficient High DC Gain Adaptive biased CMOS OTA are proposed. The proposed CMOS OTA circuit is developed using the proposed current subtractor, which provide adaptive biasing in OTA. For achieving improved DC gain, the partial positive feedback loop is used. The proposed circuits are simulated using UMC 0.18μm CMOS technology process parameters and the simulation results are presented. The layouts of all the proposed circuits are designed using Cadence Virtuoso XL Design Environment tool. The performance parameters of the proposed CMOS OTA have also been compared with the existing similar OTA circuits available in literature to demonstrate the effectiveness of the proposed circuit.