Study and Analysis of Reliability of Chip with Latest Technology

Abstract

With the growing technology, various challenges are coming to picture at SOC level with respect to functionality of the design, timing and power perspective. Reliability of a chip includes IR drop (or voltage drop) and Electromigration (or EM) observed in the chip. The IR drop further includes Static IR Drop and Dynamic IR Drop. The current flowing in the metal grid, having some resistance will result in Static IR Drop. The maximum limit of Static IR drop that will not affect the circuit or design is 10%. In the design, 15% Static IR Drop was coming due to weak metal grid. Grid weakness is defined in terms of the current carrying capacity of the metal grid. More current flowing in the design requires more metal paths. Thus, by making grid more robust, Static IR drop was brought down to 9%.

Dynamic IR Drop is high toggling cells in the design. The higher the toggle rate of the cells, the higher is the peak current in the design, resulting in higher IR Drop. The reason for Dynamic IR in this design was cluster of high toggling cells sitting near to each other. Due to this Dynamic IR was observed as 35% but the limit for Dynamic IR to occur in the chip is taken as 30%. By declustering all the high toggling cells, the Dynamic IR was brought down to 28%.

More is the EM percentage in the design higher will be the localized temperature, which may heat up the nearby metals also. Similar to Static IR and Dynamic IR, criteria for EM percentage that will not increase the localized temperature is taken as 400%. The percentage of EM observed in this design is 550% due to high output load capacitance. To meet the EM criteria, load splitting is the optimal solution in this case, which brought down the EM percentage to 380%