Design of Partially Depleted SOI MOSFET for Low Power Application

Abstract

Performance, area and power consumption is a critical concern in today’s VLSI system design. Therefore, Silicon-on-insulator wafers are used in semiconductor device applications. Silicon-on-insulator is used for a variety of applications in power switching device, semiconductor memories, high-speed bipolar circuits and micro-electro-mechanical system etc. In this thesis work, 90nm bulk-Si MOSFET, partially depleted SOI MOSFET with lightly doped drain implantation and partially depleted SOI MOSFET with lightly doped drain and halo implantation has been simulated using Atlas and Athena module of Silvaco tool. SOI technology is well discussed in terms of its structure, advantages, characteristics, short channel effects and fabrication techniques etc. At 90nm, electrical characteristics of bulk-Si MOSFET, partially depleted SOI MOSFET with lightly doped drain implantation and partially depleted SOI MOSFET with lightly doped drain and halo implantation has been found out. Effect of different parameters such as gate oxide thickness, channel doping and halo implantation on threshold voltage and off current of partially depleted SOI MOSFET has been studied. Further, a capacitorless 1T DRAM cell has been designed using 90nm partially depleted SOI MOSFET with lightly doped drain implantation. Also, working of capacitorless 1T DRAM using partially depleted SOI MOSFET as access transistor has been shown. Leakage current in partially depleted SOI with lightly doped drain implantation has been reduced by using process technique, called halo implantation. The leakage current in partially depleted SOI MOSFET with lightly doped drain and halo implantation has been reduced by about 90% as compared to partially depleted SOI MOSFET with lightly doped drain implantation.