Design of NMOS Four Quadrant Analog Multiplier

Abstract

Analog multipliers found its wide spread applications in the era of signal processing, neural networks as well as frequency doublers, RMS circuits and phase detectors (Phase lock loop). High Input signal range, linearity and high operating frequency are the prime issues for the multipliers in conventional applications like modulation circuits. Power consumption is the criteria in case of massive parallel processing based networks. This thesis explains the design process of four-quadrant multiplier designed using eldo simulator at 0.35µm technology which could be able to address the challenges mentioned above. Initially, different multipliers architectures have been discussed. A NMOS based four quadrant voltage mode multiplier is designed using differential summing, squaring and amplifier circuits and is simulated for DC, transient and AC analysis to confirm the correctness of the design. In addition to these, bandwidth, mismatching of transistors and active area of the chip are also optimized. The final design of multiplier has ±0.66V input range, 67.79MHz bandwidth, 1.51mW power consumption with 0.691V bias voltage. Special layout techniques like interdigitation and common centriod methods can be utilized to reduce mismatches between transistors and effects of process variations are minimized.