Design and Analysis of Low Dropout Voltage Regulator for Ultra-Low-Power Applications

Abstract

A system-on-chip (SoC) with near-threshold supply voltage operation has received a significant amount of attention. Due to its high energy-efficiency, it supports a number of low power emerging applications such as wireless sensor networks and Internet-of-Thing devices. By integrating diverse digital, analog, mixed-signal, and power delivery subsystems, these SoC designs must harness dozens of voltage domains to push the boundaries of power efficiency, performance, and robustness. A low dropout (LDO) regulator is a key building block for creating voltage domains on a chip due to its high-power density. In particular, its digital implementation, i.e., digital LDO, recently has emerged as a popular topology since it can support a wide range of input voltage from sub-threshold to near-threshold voltage domains, while conventional analog LDOs become less effective. However, the existing digital LDO designs use full-custom comparators to compare reference and output voltages, which make the designs partially synthesizable. Aside from that, most digital LDOs require a huge off-chip output capacitor to stabilize the output voltage. Also, digital LDOs require high clock frequency (fCLK) to provide fast-transient response; however, such solutions inevitably increase power dissipation. This thesis presents my research on digital LDOs for ultra-low-power applications. My research focuses on CMOS standard-cell-based implementation of LDO. To implement the entire digital LDO using CMOS standard cells, a fully synthesizable comparator (FS-COM) is first designed and proposed to determine the error voltage. The FS-COM can support rail-to-rail common-mode input voltages (VCM). The fast-transient response of FS-COM, even at sub-threshold or near threshold voltage levels, makes it suitable for high-speed ultra-low-power designs. A fully-synthesizable LDO is then proposed using FS-COM for applications consuming up-to tens of microamps. With a supply voltage (VSUP) of 0.5Vand a load current (IOUT) of up-to 2mA, a regulated VOUT is attained with a dropout voltage of 50mV. At fCLK = 10MHz, the proposed LDO achieves a quiescent current (IQ) and fast-TR of 2.2μA and 910ns, respectively. A maximum current efficiency (η) of 99.89% is attained with output ripples < 1mV. The last design introduces overshoot/undershoot detector and freeze-mode to achieve ripple-free output and a fast-transient response. The layouts of proposed designs are implemented using conventional synthesis and place-and-route (PnR).