APR Flow for High-Performance VLSI Blocks and Optimizing Design Metrics

Abstract

The efficiency of the physical design flow has become more and more important as integrated circuits grow into advanced technology nodes, making it harder to achieve optimal performance, power and area utilization commonly known as PPA. APR (Automatic Placement and Routing) directly impacts the design metrics like timing closure, congestion and manufacturability aspects which are the key components of this process. This paper provides a brief overview of the APR flow, requirement for optimizing the design metrics and the tools used for this process.