Modified 10 Coded Test Data Compression Technique for System on Chip

Abstract

SoC testing has become increasingly complex nowadays. With the application of large test data, there is an increase in test time. The testing cost of a SoC is directly proportional to test data volume. Large test data volume also leads to increased automatic test equipment (ATE) memory requirements. International Technology Roadmap for Semiconductors (ITRS) represents that there will be a need of hundreds of sub-processors for the future generation of SOC designs which will further increase the test cost. Testing involves a large amount of power dissipation. Dynamic power dissipation is the major source of power dissipation due to increased switching activity. Many techniques have been proposed till date to lessen test data volume and test power consumption during testing of an SoC. But till date, there has always been a tradeoff between power consumption and compression in test data volume. The objective of this work is to compress the test data by modifying the 10C coding scheme. In this thesis report, modified compression technique is proposed for testing different SoC’s while taking test power into consideration. This problem can be optimized by first double reordering based on hamming distance. Secondly, apply modified 10C compression scheme on the reordered test set taking into account the maximum probability of frequency of occurrence of combinations. Testing of compression mechanism has been carried out on ISCAS’s benchmark circuits with achieved compression efficiency up to 49.18% and power consumption reduced by 72.34%.