Design and Simulation of Low Power and Stable 7T SRAM Cell

Abstract

As the feature sizes decrease, understanding of circuit variations becomes essential to effectively design robust circuits. As the memory devices and circuits are further scaled down various issues come up like stability, leakage and area. It is important to continue looking for alternatives to improve upon the available research. To overcome these challenges, researchers have proposed different topologies for SRAMs with 5T ,7T, 8T and 9T SRAM designs. These designs improve the cell stability but suffer from bitline-leakage, noise, placing constraints on the number of cells shared by each bitline. These designs also have substantial area overhead when compared to the traditional 6T design except the 5T SRAM design. In this work, the published SRAM designs are characterized using commercial CMOS 180 nm models and are compared based on critical SRAM parameters like read stability, write stability, bitline leakage and read-write delays. Furthermore, a 7T SRAM Cell design is proposed that enhances data stability and simultaneously addresses the bitline leakage problem. The goal is to improve the parameters of the cache memory array without adding too much area overhead. The design metrics for the 7T cell are discussed in detail and performance and stability are evaluated. It is shown that although the area of the memory array has increased by 13% but the performance has increased considerably. The new cell also has 30% lower total leakage current and 50% more stability during read.