Design of Low Power and High Fault Coverage Test Pattern Generator for BIST

Abstract

Low Power consumption has become increasingly important in hand-held communication systems and battery operated equipment, such as laptop computers, audio and video-based multimedia products, and cellular phones. For this new class of battery-powered devices, the energy consumption is a critical design issue since it determines the lifetime of the batteries. Thereby, the reduction of the energy consumption is becoming one of the most growing topics of interest in the electronics industry and one of the most challenging areas of research in this domain. In the same time, modern design and package technologies make external testing more and more difficult, and built-in self test (BIST) has emerged as a promising solution to the VLSI testing problem. BIST is a design for testability methodology aimed at detecting faulty components in a system by incorporating test logic on-chip. BIST is well known for its numerous advantages such as improved testability, at-speed test of modules, no need for automatic test equipment, and support during system maintenance. Moreover, with the emergence of core-based “system-ona- chip” designs, BIST represents one of the most favourable testing methods since it allows preserving the intellectual property of the design. A new low power test pattern generator using a linear feedback shift register (LFSR), called LP-TPG, is presented to reduce the average and peak power of a circuit during test. The correlation between the test patterns generated by LP-TPG is more than conventional LFSR. LP-TPG inserts intermediate patterns between the random patterns. The goal of having intermediate patterns is to reduce the transitional activities of primary inputs which eventually reduces the switching activities inside the circuit under test, and hence, power consumption. The random nature of the test patterns is kept intact. The area overhead of the additional components to the LFSR is negligible compared to the large circuit sizes. The experimental results are shown for ISCAS85 benchmarks, confirming up to 63% and 27% reduction in average and peak power, respectively.