Design of Two-Stage Fully-Differential Inverter-Based Self-Biased Gain-Boosted Amplifier in 0.18 µm CMOS Technology
| dc.contributor.author | Sharma, Akhil | |
| dc.contributor.supervisor | Agarwal, Alpana | |
| dc.date.accessioned | 2016-08-26T04:55:07Z | |
| dc.date.available | 2016-08-26T04:55:07Z | |
| dc.date.issued | 2016-08-26 | |
| dc.description | M.Tech. (VLSI Design) | en_US |
| dc.description.abstract | This thesis work describes a two-stage fully differential gain-boosted CMOS amplifier consisting of two self-biased inverter stages. The self-biasing avoids the use of external biasing circuitry, thus reduces the die area and the power consumption. Although it relies on a class A topology, it achieves higher efficiency and comparable to the best class-AB amplifiers. In the present work regulated cascode technique has been employed for gain boosting. The miller compensation is also applied to enhance the phase margin. The circuit has been designed and simulated in 1.8 V 0.18 µm CMOS technology. The simulation results show a high DC gain of 100.7 dB, Unity Gain Bandwidth of 107.8 MHz and Phase Margin of 66.7o, which makes it suitable for the pipelined ADCs. | en_US |
| dc.description.sponsorship | Department of Electronics and Communication Engineering, Thapar University and Department of Electronics and Information Technology (GoI) through SMDP C2SD Project. | en_US |
| dc.identifier.uri | http://hdl.handle.net/10266/4156 | |
| dc.language.iso | en | en_US |
| dc.subject | Fully Differential | en_US |
| dc.subject | Gain Boosted | en_US |
| dc.subject | Inverter based | en_US |
| dc.subject | CMOS Amplifier | en_US |
| dc.title | Design of Two-Stage Fully-Differential Inverter-Based Self-Biased Gain-Boosted Amplifier in 0.18 µm CMOS Technology | en_US |
| dc.type | Thesis | en_US |