Ground bounce minimization in low power MTCMOS circuits

Abstract

Recently, there has been rapid progress in personal communication services (PCS) based on battery drives, including digital cellular phone, personal digital assistants, notebook and computers. In order to promote this development, low power design is essential to achieve the miniaturization and long battery life. Multiple Threshold CMOS (MTCMOS) power gating is one of the most effective techniques in reducing leakage power, which increases exponentially with device scaling. However, this technique suffers a major problem called ground bounce noise during active to sleep mode transition. During mode transition, a sudden current surge flows through parasitic inductance connected to power and ground pins due to packaging which causes voltage fluctuation or ground bounce on the supply line which affect the nearby circuits operating normally. This dissertation is a comprehensive record of the work done toward minimization of ground bounce noise in the Digital VLSI Circuits. We analyzed this ground-bounce noise and reduced it with novel power-gating structures that utilize holistic integrated device circuit- architecture approaches. The efficiency of the technique has been tested on 16 bit ripple Carry Adder in 180nm CMOS technology. Furthermore performance of Ground bouncing reduction techniques have been compared with the available techniques for reducing ground bounce, not only for the ground bounce but also with respect to other parameter like leakage power, Energy Overhead, the maximum peak of current surge, Wakeup Delay and Area overhead. It is evident from the simulation result that there is approximately 92% of reduction in ground bounce from the proposed technique.