CMOS Low Noise RF Amplifier Design and Parameter Estimation Using ANN

Abstract

In recent years, down-scaling in CMOS advanced technologies has provided high performance in digital circuits and reduced costs thereby meeting to a large extent the increasing demand of wireless communication products. With this technology advancement, the unity-current gain frequency of CMOS technology is now over several tens of GHz making the realization of system-on-chip solution possible which in turn, further reduces the cost. The demand of highly integrated CMOS RF building blocks with low noise has served as a motivation for present research initiative. Therefore, it becomes necessary to explore the area of low noise and power CMOS RFIC design for applications in a LOW NOISE AMPLIFIER. A low-noise amplifier (LNA) is an electronic device used to amplify possibly very weak signals (for example, captured by an antenna). It is usually located very close to the detection device to reduce losses in the feedline. It is necessary for an LNA to boost the desired signal power while adding as little noise and distortion as possible, so that the retrieval of this signal is possible in the later stages in the system. A good LNA has a low noise figure (NF), a large enough gain and should have large enough intermodulation and compression point. LNA is designed using the Cadence Spectre_RF tool on UMC 0.18µm technology to validate their performance. The various topologies of LNA are designed and simulated in this thesis report. The various topologies like single-ended LNA, differential LNA and CRLNA are compared in terms of their performance parameters. This thesis also reports a novel endeavour in the form of an Artificial Neural Network (ANN) model which estimates different amplifier parameters based upon the obtained simulation results, thereby, providing an alternative to the popular simulation tools which are based on complex analytical and mathematical models.