A Novel all Digital 4-bit Flash ADC

Abstract

In recent years, Digital signal processing has progressed drastically with technology. However it with not provide the same level of advantage as of analog IC. To get the more accurate output, we will process the signal into digital form. Most of the communication need wireless signal i.e. digital signal but in the real world, all outputs are analog in nature so we have to convert analog signal to digital signal to communicate to the real world. For an efficient system, all blocks should be fast. This fact has led researchers to develop and implement high speed analog-to- digital converters (ADCs) with low power consumption. This research work describes the highly digital 4-bit 200-MS flash ADC whose major part can be synthesized from verilog code thus achieving low power and reduces the much needed time to market. The comparator circuit is created by CMOS using Inverter and NAND-NOR logic gates. The proposed circuits are simulated in Cadence Virtuoso Analog Design Environment and Anolog Mixed Signaling (AMS) in SCL 180 nm CMOS technology with a supply voltage of 1.8V. Also, the proposed digital-in-process flash ADC has been proposed. The SNDR, SNR and SFDR equal to 24.4566 dB, 25.9533 dB and 30.2788 dB. It provides an effective number of bits (ENOB) equal to 3.7702. The DNL of this flash ADC is +0.25 LSB and INL is +0.6 LSB.