FPGA implementation of 2^r variable RNS scaler for extended four moduli sets

Abstract

Variable scaling by power-of-two factor is the backbone operation of floating point arithmetic. It is commonly used in fixed-point digital signal processing (DSP) system for overflow prevention. This operation can be easily performed in binary number system, but it is very difficult to perform in Residue Number System (RNS). In this thesis, 2^r variable RNS scalers are designed for important classes of moduli sets that have large dynamic range. These important classes of moduli sets include traditional three moduli set {2^n-1, 2^n, 2^n+1} and any extended power-of-two moduli sets m4 ({2^n-1, 2^n, 2^n+1, m4}). In this approach, scaling is done by combining both Chinese Remainder Theorem (CRT) and mixed radix conversion (MRC). Scaling is completely done in RNS domain, no reverse conversion or forward conversion required in this approach. Simple, memory less VLSI architectures are proposed based on the obtained formulation. In hardware design, carry save adders with end around carry (CSA w EAC), carry save adder with complementary end around carry (CSA w CEAC), shifters different modulo adders and a modulo adder circuits are used. Shifters are used to provide variable scaling in RNS. Number of bits shifted in a string are controlled by the value of r. These kind of shifter can be implemented with the help of multiplexers. These RNS scalers are synthesized and simulated using Xillinx ISE 14.5 targeting Spartan 6E FPGA device The relative assessment shows that these architectures provide variable power-of-two scaling but, the increment in area leads to increment in cost, also there is increase in delay as compared fixed scaling techniques. However, this scaler provide wide range of scaling options so that these limitations can be neglected.