Design, Analysis and Simulation of Single and Multifin Trigate Finfet Structure and Cmos Implementation of Finfets

Abstract

According to Moore's law scaling of CMOS technologies beyond 22nm is limited by factors like excessive power consumption, process variation effects and other short channel effects(SCEs) like Drain Induce Barrier Lowering(DIBL), Gate Induce Drain Leakage(GIDL) and Vth roll off. Double Gate MOSFETs(DG MOSFET) are one of the solution to these SCEs but due to fabrication difficulties like misalignment of top and bottom gates etc. DG MOSFETs are replaced by FinFET. FinFET device have reduced SCEs due to their 3D structures like Double Gate FinFET(DG FinFET) and TG FinFET(TG FinFET). In this dissertation the current flow in DG MOSFETs, DG FinFETs and TG FinFETs has been analyzed. For the simulation of modelled and designed structure Matlab R2007b and Cogenda Visual TCAD 1.8.0.2 tool has been used The 3D effects due to active top gate in TG FinFET has also been analyzed and a depletion charge based current model considering 3D effects has been proposed. The agreement between the simulated and modeled results of current , supports the good accuracy of the proposed model. Further the most leaky path in subthreshold region and strong inversion region has been studied along with corner effects in TG FinFET and multi fin FinFET. Analysis of the impact of silicon body thickness over short channel effects and the comparison of multi fins and single fin FinFETs has been done. Next a CMOS inverter has been designed by using single fin n-channel FinFET and Double fin p-channel FinFET. A ring oscillator has been designed using these CMOS inverter.