DESIGN AND VERIFICATION OF nMOSFET FOR LOW LEAKAGE AT 90nm PROCESS TECHNOLOGY

Abstract

ABSTRACT Leakage is a big challenge in planar bulk IGFET at sub-100nm technologies. The research is focused on the development of sub-100nm technology nMOSFET. Simulation of the process is carried out using Silvaco TCAD tool in Athena Atlas framework to modify physical values and obtain more accurate process parameters. Several type of leakage in a short channel MOSFET has been investigated. The most common leakage that generally occurs at sub-100nm technology MOSFETs is subthreshold leakage and gate tunneling. Several advanced method such as lightly-doped drain (LDD), halo implant and retrograde well have been applied to reduce the short channel effects. By device simulation the electrical characteristics have been obtained and further investigated. Several design analysis are performed to investigate the effectiveness of the advanced method in order to prevent the variation of threshold voltage and short channel effect of a MOSFET device. Leakage reduction from 1.9×10-9 A to 4.36×10-12 A by using halo doping and retrograde well doping has been achieved. Further the MOSFET designed has been incorporated in an inverter circuit and simulated with the help of MIXEDMODE of Silvaco. The results obtained have been compared with the simulation results of same circuit on T-SPICE of Tanner by using 90nm BSIM model. It has been obtained that the designed MOSFET is faster than BSIM model by 60%.