Study and Design of Double-Gate Junctionless MOSFET structures

Abstract

In bulk MOSFET , the problem is occurrence of short channel effects as we reduce the size of the MOSFET. One of the remedies of the issues due to scaling is modification of device structures such as Silicon on insulator (SOI) based, Double gate (DG),Multi gate(MG),Fin field effect transistor (FINFET) structures. These devices help in reducing the short channel effects of the bulk MOSFET. SOI (Silicon on insulator) based devices reduces most of the leakage mechanism such as DIBL,GIDL, drain to body leakage current etc. The multi gate structure provides better controllability of the gate voltage over drain current. The problem with multi gate MOSFETs is ultra sharp doping profile between source (drain) and body region which posses a great challenge for proper operation of high speed and low power MOSFET operation. To overcome this problem, Double gate Junction-less MOSFET can be utilized. Here, a comparative study of different nano scale JL MOSFET structure have been done. For this three JL MOSFET has been studied. The first device structure(JL 1,with uniform doping throughout the source, drain and body), the second one is(JL2, without source and drain extension) , the third one is(JL3 ,with source and drain extension having uniform doping different from the doping of the body). The transfer characteristics for these devices shows that that the drain current for uniformly doped double gate JL MOSFET (JL1) decreases at high voltage as compared to other two devices. Further due to uniform doping at the source and drain extension, there is a series resistance which further causes decrease in drain current. It has been found that with increase in gate voltage (VGS), the potential at the middle of the silicon film is found higher than the potential at the surface which indicates higher accumulation of electrons at the center as compared to surface. In the second device (JL2), the centre potential is found much higher than JL1 which gives a much higher drain current. Though sub-threshold slope is increased slightly but still remain near to ideal. In the third device (JL3) , the centre potential is further increased but its SS slope remains the same as JL2. Further the CMOS inverter circuit utilizing these three NMOS devices (JL1,JL2,JL3) has been simulated on TCAD tool and comparison of VTC curve has been done. It is found that the high noise margin is much improved in JL3 as well as the transition time is much less than other two device structures. The Visual TCAD version 1.8 tool is used for validating the results.