Implementation Of Reduced Ordered Binary Decision Diagram For Feature Optimization

Abstract

The increasing speed and complexity of today’s designs implies a significant increase in the power consumption of very-large-scale integration (VLSI) chips. To meet this challenge, researchers have developed many different design techniques to reduce power. For verification and checking of various hardware circuits, symbolic checking has been successfully applied and the Binary Decision Diagram representation is the core technology underlying this success and is one of the most popular data structures to represent Boolean functions. Boolean functions can be graphically manipulated to reduce the number of nodes, hence the area, when implemented as Binary decision diagrams. In BDD, the area and power consumption is determined by the total number of nodes. As number of nodes reduces, area reduces and hence it also reduces the power. A proper polarity selection of the sub-functions can not only reduce the number of BDD nodes, but also the switching activity. To optimized BDD, we have calculated the switching activity of the circuit. Also, ordering of BDD nodes plays a very important role. Most of the algorithms for variable ordering of OBDD have focus on area minimization. Hence, for minimizing the power consumption, suitable input variable ordering is required. So, GA has been applied to find an optimal variable order that minimizes the size of BDD. Moreover, GA has been compared with various algorithms namely branch and bound algorithm, scatter search algorithm. Experimental results showed an average power reduction of 24.5 using GA and GA found to give best results in terms of power and accuracy.