Tackling EM effects during Layout Development in Custom Compiler

Abstract

Fixing electro migration (EM) violations towards end of the design cycle always poses a high risk to delivery schedules. Hence a mechanism is required to check and fix EM during the layout design phase. This paper addresses this challenge in two parts. In the first part, we describe how we have incorporated Custom Compiler’s In-Design EM Reporter Tool in our design phase and quantify the reduction in the number of EM violations seen during Sign-off and how this contributes to faster turn-around. In the second part, we describe the on-going collaboration with Synopsys to route the design with EM awareness. This is targeted for nets which are auto-routed, primarily power nets and signal nets that take a regular pattern. This involves automatic invocation of EM Reporter tool in the background and assignment of required widths to the automatic routing engine, thus resulting in EM clean routes by construction.