Upgradation of Design for Testability (DFT) Analysis Flow

Abstract

The work proposed in this thesis was done at ST Microelectronics Pvt Ltd, Greater Noida, U.P, India with Design Support and Methodology (DSM) team at Home Video Division (HVD). This team comprises of ex-designers who are now entrusted to develop and maintain the design flow, as used by HED designers worldwide. They are looking into full spectrum of Electronic Design Automation (EDA) flow. One of such EDA tools is TetraMax which is a high speed, high capacity test validation and pattern generation tool

The proposed work deals with the study of design flow using DFT Compiler and TetraMax ATPG tool and consequent upgradation of Design for Testability (DFT) analysis flow at HVD. This is required to maintain synchronous methodology during TetraMax run across various designs as well as various sites of ST Microelectronics all over the world. In the present work, we propose to develop internal STB tool which would uniquify the DFT procedures. The tool proposed is expected to check the design for testability after first synthesis itself so that DFT issues are discovered well in advance in the development of a design. In addition, customized test reports generated by the tool will help the designer to identify where he can simplify logic cones and do a specific design optimization. Therefore this will prove to be of great help to backend designers who can use it to discover DFT issues well in advance in development process of a design.