Design of CMOS Oscillator

Abstract

Non-Volatile Memories (NVM’s) are an indispensable part of every System-on-Chip (SoC) for retaining the data when the power goes off. The large inaccuracy in oscillation frequency will result in unreliable modify operation and may cause failure in read-write operations. The memory operations do need the on-chip generation of high voltage by charge pump and to drive it the clock is used. The generally utilized high exactness clock references are acknowledged by crystal oscillators, as they are resistant to the process, voltage and temperature variations, however coordinating those alongside on-chip circuits can build the general expense and power of the framework. Clearly, it is important to explore the high accuracy on-chip clock generation strategies for low cost as well as low power applications. In this dissertation, a comparative study of CMOS Oscillator and a unique design is presented. A 98MHz, conventional five stages Oscillator is compared to proposed current-starved ring oscillator of 98MHz., 40μW-65μW of power dissipation, approx. ±15%, frequency Variation within the temperature range of -40° to 150°C and supply voltage variation of ±10%, across all process Corners. CMOS oscillators are presented in 90nm BCD10 Technology for low power application. The presented PVT compensated oscillator consumes significant lesser power as well as area compared to traditional crystal counterparts. A trimming bit is used for making it compensated across temperature and process. The frequency reference is tried to be made immune to large supply variations