Temperature Dependent Performance Analysis of Single Wall Carbon Nanotube as VLSI Interconnects

Abstract

World is changing rapidly and is becoming a better place to live in with the advancement in technology. With the up gradation of electronic devices into smaller and faster phases, the associated complexity that increases with the increase in packing density and functionality of circuits, certain issues related to area and power consumption are faced. One certain issue that comes into scene is the delay associated with the interconnect material. Propagation delay of interconnect is an important parameter which helps in determining the performance of high speed VLSI circuits. With the advancement in technology, certain problems like electromigration, surface roughness and grain boundary scattering prevail in copper; so CNTs are introduced with excellent thermal conductivity and current carrying capacity at scaled technology nodes. Due to high resistance in isolated ones; SWCNT bundle are used comprising of number of parallel isolated CNTs. In this dissertation report, the performance of copper and CNT interconnect are studied and compared at 32nm and 22nm technology. The effects of various parameters like length and diameter of interconnect, number of repeaters and size of driver transistor and temperature have been analyzed. Delay analysis is done using SPICE simulation. The thermal heating effects are one of the most important and indispensable consideration of VLSI designers responsible for maximum IC failures at increased packing densities of the circuits. Different types of electron- phonon scattering mechanisms in metallic SWCNT bundle interconnects that reduce electron mean free path have been studied. Results reveal that resistance of interconnects thus increases due to rise in temperature and thereby delay increases. However, the delay of copper is always more than CNT bundle at raised temperatures. SWCNT bundle gives better result than copper and provides appropriate solution as an interconnect material in deep submicron technology at semi-global and global interconnect lengths for high speed circuits.