Modeling and Performance Analysis of Mixed CNT Bundle as VLSI interconnect

dc.contributor.authorThakur, Arvind
dc.contributor.supervisorSandha, Karmjit Singh
dc.date.accessioned2017-08-24T05:14:28Z
dc.date.available2017-08-24T05:14:28Z
dc.date.issued2017-08-28
dc.descriptionMaster of Technology -VLSI Designen_US
dc.description.abstractThe bottleneck in the VLSI circuit is an interconnect delay. With the downscaling in the technology nodes, interconnect delay dominates the gate delay. In the semiconductor industry device size is decreasing year by year and the numbers of components on the integrated chips are increasing, each year. With the scaling in the technology nodes, it was observed by the researcher that there is a problem of grain boundary scattering, surface scattering and electro migration in Copper (Cu) as interconnect. So there is great necessity of alternative material which is better than Cu interconnect. As the Cu interconnect is prone to issues with downscaling in technology, Carbon nanotubes (CNTs) are one of the good selection to Cu for VLSI interconnect as it has high current carrying capacity and large thermal conductivity. In this research work, mixed CNT bundle as an interconnect for very large scale integration (VLSI) circuits is analyzed. Using the hierarchical modelling, MCC model of mixed CNT is developed. The mixed CNT bundle contains both MWCNTs and SWCNTs. The performance of mixed CNT bundle is better than MWCNT bundle at intermediate, global and local levels. The propagation delay and power delay product (PDP) is estimated at intermediate, global and local levels for mixed CNT bundle using Tanner EDA tool and simulation is done using SPICE files. Due to the insertion of SWCNTs surrounding (side-walls and corners) the MWCNT, the conductivity is increased because the SWCNTs increases the density of shells and therefore, decrease in the overall effect of resistance and inductance of MWCNTs connected vertically in parallel to each other. The structure is analyzed for different technology nodes i.e. 32nm, 22nm and 16nm at differentinterconncts lengths. Based on the comparative result, it is observed that the overall propagation delay and the power delay product (PDP) of mixed CNT are decreased as compared to SWCNT and MWCNT interconnecten_US
dc.identifier.urihttp://hdl.handle.net/10266/4742
dc.language.isoenen_US
dc.publisherThapar Universityen_US
dc.subjectMCCen_US
dc.subjectESC modelen_US
dc.subjectMixed CNTen_US
dc.subjectPropagation Delayen_US
dc.subjectPower Dissipationen_US
dc.titleModeling and Performance Analysis of Mixed CNT Bundle as VLSI interconnecten_US
dc.typeThesisen_US

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