Study of Impact of Parameter Variations of FinFET on DIBL and Short Channel Effects

Abstract

Bulk CMOS transistor technology is facing significant challenges due to several cause such as the increasing leakage current, high power dissipation, mobility degradation and short channel effects (SCEs). When channel length shrinks, gate control over channel reduces due to various SCEs such as drain induced barrier lowering, charge sharing, and surface punch-through. Silicon on insulator technology is capable of providing increased transistor speed, reduced power consumption, fine isolation between devices, significant reduction in parasitic capacitance, and extended scalability. In this work, a thorough study of effects of parameter variations on the operation of multi gate field effect transistor has been done. For this, a triple gate FinFET structure has been design and simulated using TCAD tool. The parameters like fin-width, fin- height, channel doping and underlap length has been varied and their effects on FinFET has been observed. The simulation results show that small increase in underlap length improves the ION/IOFF ratio significantly. Further increase in fin-height, a reduction in leakage current has been observed. Also a decrease in fin-width shows a significant reduction in leakage current. All the simulations have been done on Cogenda Visual TCAD tool.