Modeling and Analysis of Temperature Dependence of Multiwall Carbon Nanotubes for VLSI Interconnects

Abstract

For nano-scaled technology nodes, the density of active devices increases for Very Large Scale Integration (VLSI) chip design. The large number of long interconnects are to be required to interface millions of active devices in an Integrated Circuit (IC). The impedance parameters of interconnects increase linearly as interconnects length increases, therefore the performance of an interconnect becomes more important compared to device performance at deep submicron technology. The present research, explores the possibilities to replace the traditional copper interconnects because its deficiencies like grain boundary, surface boundary and electromigration at nano-scaled technology nodes. Due to large electrical and thermal conductivity of Carbon Nanotubes (CNTs), CNT have been considered as alternative for long VLSI interconnects. CNTs are hollow tubes made from a sheet of carbon grapheme by rolling it up. These cylindrical shaped carbon molecules have attractive thermal and electrical properties which make it more suitable in the field of electronics, nanotechnology, optics, material science and other fields of technology. CNTs are classified as Single Walled Carbon Nonotube (SWCNT) and Multi Walled Carbon Nanotube (MWCNT) on the basis of its structure. SWCNTs are hollow tube rolled up from graphene sheets with similar diameter and SWCNT bundle consists of many such SWCNT tubes. Multi-Walled CNT (MWCNT) consists more than two rolled up hollow tubes having different diameters ranging from few nanometers to tens of nanometers. Both types of CNTs have same current carrying capacity but MWCNTs are easier to fabricate compared to SWCNTs because of its better control on the growth process. Such advantages of MWCNT attract most of the researcher towards the analytical modeling and performance analysis of MWCNT based interconnects for nanoscaled technology nodes. The high performance VLSI integrated circuit design at nanoscaled technology nodes has large variations in their performance under variable thermal environment conditions for its different applications. Therefore, it is required to include the influence of thermal variations to estimate the accurate performance of an integrated circuit (IC). The works presented in thesis, proposed to estimate the influence of temperature on the performance of MWCNT bundle interconnects for global length. Temperature dependent equivalent circuit model is presented to evaluate the impedance parameters of MWCNT bundle interconnect which includes the various electron–phonon scattering mechanisms as a function of temperature. The impact of acoustic and optical and zone boundary scattering on electron-phonon scattering mechanism is analyzed resented along with mathematical equations. These mathematical expressions are incorporated the influence of temperature on Mean Free Path (MFP) of MWCNT. Further, effective MFP used to estimate the temperature dependent impedance parameters of an individual shell of MWCNT. All the individual shells of MWCNT bundle have been considered as parallel shells for temperature dependent equivalent model of MWCNT bundle. By using the temperature dependent impedance equivalent circuit model of MWCNT bundle, the impedance parameters have been calculated for global interconnects at 32nm, 22nm and 16nm technology nodes for temperature range of 200K to 450K. For increasing temperature, MFP of shells decreases because of increasing collision rate with in MWCNT. The increase in collision rate is due to electron-phonon acoustics and optical and zone boundary scattering mechanism. The decreased MFP with increasing temperature, influence the resistance for MWCNT shells. Therefore, this change in resistance has considerable effect on the performance in terms of delay, power and PDP for the MWCNT bundle interconnects at nano-scaled technology nodes for global interconnects lengths. Based on proposed temperature dependent impedance model, the impedance parameters of MWCNT interconnect is calculated for global interconnects at three different technology nodes (32nm, 22nm and 16nm). All interconnects technology parameters are calculated using the data obtained from ITRS 2013 version. The results show that the resistance of MWCNT bundle increases with increasing temperature from 200K-450K for all the global interconnects length under consideration at 32nm, 22nm and 16nm technology nodes. To estimate the performance of MWCNT bundle interconnects, signal delay, power dissipation and Power Delay Product (PDP) is simulated based on temperature dependent model that results in, improvement in the delay, power and PDP estimation accuracy compared to temperature independent model. The results revealed that delay and Power Delay Product of MWCNT bundle interconnects increases with increasing temperature from 200K to 450K for global level interconnects at three different technology nodes i.e. 32nm, 22nm and 16nm. Further, the temperature dependent analytical delay model has been presented for MWCNT interconnects and analytical results are compared with the simulated results. The results show that the analytical results are in similar trend with the simulated results. The trend of both results shows that the delay is increases with rise in temperature for three technology nodes i.e. 32nm, 22nm and 16nm. Therefore, it is concluded from the results that for high performance IC design, under variable thermal environments need to be considered the impact of temperature to estimate accurate performance. A similar analysis is performed for SWCNT bundle interconnects and copper interconnects and compared with MWCNT bundle interconnects. Comparative results revealed that delay, power and Power Delay Product (PDP) is increased with rise in temperature ranging from 200K to 450K for MWCNT bundle, SWCNT bundle and copper interconnects. It has also been observed that MWCNT bundle interconnects gives better performance in terms of delay, power and PDP as compared to SWCNT bundle interconnects for global levelinterconnects at 32nm, 22nm and 16nm technology nodes under thermal variable condtions.