Design and Analysis of Fully Differential Double-Tail Dynamic Comparator Using Charge Sharing Technique

Abstract

In today’s fast moving digital world, it becomes necessary to come up with an innovation in digitization constantly. An important component in a semiconductor Integrated Circuit (IC) industry is an Analog-to-Digital Converter (ADC). Various portable devices which are used in communication systems, precision data acquisition systems, medical instruments, etc. require ADCs which consumes low power and provides high speed. The comparator is a pivotal building block in any ADC architecture. To meet the demand for low-voltage/low-power and high speed ADCs a new fully differential double-tail dynamic comparator using charge sharing technique (FDDCCST) is proposed in this research work. To lower the power consumption and speed up the comparison process, a charge sharing technique is employed in the latch stage of the proposed FDDCCST. In the proposed FDDCCST differential pair and double-tail comparator topologies are combined to minimize the offset voltage. Also, a detailed analysis of the proposed FDDCCST which includes delay analysis, power analysis and mismatch analysis is explained in this thesis. The proposed FDDCCST has been designed and simulated in 0.18μm CMOS technology with supply voltages of ± 0.75 V using Cadence Virtuoso Analog Design Environment. Simulation results verify that the proposed FDDCCST has worst case delay of 0.219 ns with power dissipation of 156.3 μW. The offset voltage is 0.184 mV with 1σ deviation of 7.65 mV. The proposed FDDCCST is faster, power efficient with low offset voltage than the existing dynamic comparator structures.