Analysis and Design of CMOS Comparator based on gm/Id Approach for CBSC Circuits

Abstract

The design of high gain op-amps for switched-capacitor circuits has become increasingly challenging with the migration of designs to scaled CMOS technologies. In order to eliminate the use of op-amps in sampled data systems and thus avoid several delicate trade-off between the designs, a new class of Comparator-Based Switched Capacitor (CBSC) has been introduced, that replaces op-amp in sampled data systems with the comparator and a set of current mirrors. CBSC circuits have lower power consumption, compared to op-amp based system and avoid several delicate trade-off of the op-amp circuits. CBSC can be used in switched capacitor filters, pipelined ADC & integrator in sigma-delta ADC etc. A critical circuit in the CBSC method is the virtual ground detection comparator. The comparator used must have high speed and low offset, so as to avoid the delay in virtual ground detection. The role of the virtual ground detection by the comparator is of critical importance to the accuracy of the CBSC circuits.The major objective of this work is to understand the concepts behind the Comparator-Based Switched Capacitor (CBSC) technique for scaled technologies and designing a high speed and low offset comparator for the CBSC circuits.The gm/Id technique is also adopted in this work, to help us designing analog circuits in submicron technologies. This work also compares the designing of high speed and low offset comparator using gm/Id technique with that of conventional design technique. The design was simulated in UMC 0.18μm CMOS process with power supply of 1.8V in Cadence Analog Design environment.